`timescale 1ns / 1ps
//
// CSE141L Lab 2
// University of California, San Diego
// 
// Written by Donghwan Jeon, 5/18/2007
// Modified by Vasileios Kontorinis 10/09/2009
//

// Data Memory Module
//
// parameters:
// 	A_WIDTH: SRAM address width
// 	D_WIDTH: data width

module dmem#(parameter A_WIDTH = 8, D_WIDTH = 8)
(
	input  reset,
	input  clk,
	input  dmem_read_write_req_in,
	input  dmem_write_en_in,
	input  [A_WIDTH-1 : 0] addr,
	input  [D_WIDTH-1 : 0] din,
	output [D_WIDTH-1 : 0] dout,
	output refused
);

reg  [2:0] counter;
reg  refused_r;
reg  dmem_read_req_r;
reg  dmem_read_write_req_r;
wire refused_w;
wire [D_WIDTH-1 : 0] dout_temp;
wire write_control;


//assign write_control = dmem_read_write_req+in & dmem_write_en_in & ~refused_w;
assign write_control = dmem_read_write_req_in & dmem_write_en_in;
assign refused = refused_r & dmem_read_write_req_r;
//assign refused_w = counter[2] & counter[1] & counter[0];
assign refused_w = 0;
//assign dout = (refused | ~dmem_read_req_r)? {(D_WIDTH){1'b1}} : dout_temp;
assign dout = (~dmem_read_req_r)? {(D_WIDTH){1'b1}} : dout_temp;

d_mem_8_256 mem
(
	.clka(clk),
	.dina(din), // Bus [7 : 0] 
	.addra(addr), // Bus [7 : 0] 
	.wea(write_control), // Bus [0 : 0] 
	.douta(dout_temp)  // Bus [7 : 0]
);

always@(posedge clk)
begin
	 if (reset)
			counter <= 3'b0;
	 else
			counter <= counter + 1;
	 refused_r <= refused_w;
	 dmem_read_write_req_r <= dmem_read_write_req_in;
	 dmem_read_req_r <= dmem_read_write_req_in & ~dmem_write_en_in;
end	

endmodule
